1. Field of the invention
The present invention relates to a phase-change memory device and method of manufacturing the same, and more particularly to a phase-change memory device and method of manufacturing the same, which can reduce a contact area between a bottom electrode and a phase-change layer, thereby reducing quantity of current.
2. Description of the Prior Art
As generally known in the art, memory devices can be classified into Random Access Memories (RAMs) which are volatile and lose stored information when power supplied thereto is interrupted and Read Only Memories (ROMs) which are non-volatile and keep information stored therein even when power supplied thereto is interrupted. The volatile RAMs include Dynamic RAMs (DRAMs) and Static RAMs (SRAMs) and the non-volatile ROMs include flash memory devices such as Electrically Erasable and Programmable ROMs (EEPROMs).
However, the DRAM, which is an excellent memory device as is well known in the art, requires a high charge-storage capacity for its periodic refresh operation, which consequently requires an increase of a surface area of an electrode, thereby making it difficult to achieve a high circuit integration. Further, the flash memory device requires higher operation voltage than a power supply voltage in relation to the lamination structure of two gates. Therefore, in the flash memory device, a separate voltage-booster circuit is necessary in order to obtain a voltage necessary for write and erase operations. In this regard also, the flash memory device disturbs high integration of a circuit.
Therefore, researches have been made into the development of a new non-volatile memory device capable of achieving high-integration and having a simple construction, one proposal for which is a phase-change memory device (phase-change RAM).
In the phase-change memory device, a phase-change layer interposed between a top electrode and a bottom electrode experiences a phase change from a crystalline state to an amorphous state by current flow between the top electrode and the bottom electrode, so that the phase-change memory device discriminates the information stored in the cell by means of resistance difference between the crystalline state and the amorphous state.
In other words, the phase-change memory device employs a chalcogenide film as the phase-change layer. The chalcogenide film is a compound material layer (hereinafter, referred to as “GST layer”) consisting of germanium (Ge), stibium (Sb), and tellurium (Te) and causes a phase change between the crystalline state and the amorphous state by an applied current or Joule Heat. Here, the phase-change layer has a higher specific resistance in the amorphous state than in the crystalline state. Therefore, whether the information stored in the phase-change memory cell refers to a logic ‘1’ or ‘0’ can be determined by detecting the current flowing through the phase-change layer in the ‘read’ mode.
FIG. 1 is a sectional view of a conventional phase-change memory cell.
In the conventional phase-change memory cell as shown in FIG. 1, a interlayer dielectric 5 is formed on a bottom electrode 3 formed on a semiconductor substrate 1. Then, the interlayer dielectric 5 is etched to form a contact plug 7 electrically connected with source regions and a phase-change layer 9 is then formed on the resultant substrate having the contact plug 7 formed thereon. Thereafter, a top electrode 11 is formed on the phase-change layer 9.
When voltage is applied in order to program the phase change memory cell, heat is generated at an interface between the phase-change layer 9 and the contact plug 7, so that a portion 9a of the phase-change layer 9 is transformed into an amorphous state. The heat generated at the periphery C of the contact plug 7 and the phase-change layer 9 may be spread to the neighboring contact plug 7 and be unable to reach the temperature necessary for the phase change. Therefore, even after the phase-change layer is phase-changed into an amorphous state, there may remain an abnormal region (which is not changed into the amorphous state) at the periphery of the phase-change layer 9.
Further, in the ‘read’ and ‘write’ operations of the phase-change memory device, the large contact area between the bottom electrode and the phase-change layer requires an increased quantity of current for the phase change, thereby having a bad influence on the speed of the phase-change memory device.